In recent years, reduced power consumption of a semiconductor device (LSI) has been further strongly demanded. Accordingly, power consumption is reduced by lowering an operating frequency in a case where a load decreases. Further, it is desired that power consumption is reduced with satisfaction of demanded performance in spite of manufacturing variability, temperature change, and so forth.
For example, in a case where a threshold value (Vth) of a transistor increases due to the manufacturing variability, an operation rate of the transistor becomes slow, and a signal propagation delay of a circuit increases. Thus, it is desired that a high power supply voltage VDD is set to decrease the delay so that a demanded operating frequency is satisfied.
On the other hand, in a case where the threshold value (Vth) of the transistor decreases due to the manufacturing variability, the operation rate of the transistor becomes fast, and a leakage current amount of the circuit increases, resulting in an increase in energy consumption. Thus, it is desired that a low power supply voltage VDD is set to reduce the energy consumption of the circuit to a limit in which the demanded operating frequency is satisfied in spite of the delay.
Accordingly, a power supply voltage is controlled in accordance with the operating frequency, the manufacturing variability, and the temperature change, and energy consumption per performance is thereby reduced while demanded performance is satisfied. This is referred to as an adaptive voltage scaling (AVS) power management technology.
There are cases where the AVS power management technology is applied to the entire circuit of the semiconductor device and where the semiconductor device is divided into a plurality of circuit blocks and control of power supplies to the circuit blocks is performed while including distribution of loads to the circuit blocks. In order to control the power supplies to the circuit blocks, independent power supplies are provided for the circuit blocks, and at least one of the circuit blocks individually controls the power supply voltage. In the following description, a description will be made about a case where the AVS power management technology is applied to the entire circuit or the single circuit block.
In a common AVS management technology, the power supply voltage is lowered as much as possible in a range in which the circuit blocks normally operate. A determination of whether or not the circuit normally operates is made by measuring the delay of the circuit, for example. In general, the delay of the circuit is measured by providing a delay monitor circuit that has a ring oscillator and a counter and measuring a change in a frequency of the ring oscillator that changes in accordance with the power supply voltage by counting a change in an output signal. Then, a determination is made whether or not the delay that is obtained from a count value is smaller than the delay with which the demanded operating frequency is satisfied.
Examples of related art are Japanese Laid-open Patent Publication Nos. 2003-115750, 08-272491, 2003-194858, and 2010-098202; Muramatsu Atsushi, et al., “12% Power Reduction by Within-Functional-Block Fine-Grained Adaptive Dual Supply Voltage Control in Logic Circuits with 42 Voltage Domains”, ESSCIRC, 2011; and Fuketa Hiroshi, et al., “12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2 V to 310 mV enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics”, International Symposium, pp. 163-168, ISLPED, 2011.
It has been known that when the power supply voltage reaches a very low voltage area (0.5 V or lower), an influence of local variation (random variation) of the threshold value Vth of the transistor becomes more significant and increases a possibility that a flip-flop does not operate (malfunctions) in an individual cell. However, an above method that uses the delay monitor circuit may not detect a phenomenon in which the flip-flop malfunctions at a low power supply voltage. On the other hand, in a case where the power supply voltage is low, an acceptable delay becomes large because the operation rate of the circuit is slow.
Thus, there is a case where the power supply voltage lowers to a voltage at which the circuit does not operate when the demanded operating frequency lowers (for example, several hundred kHz or lower) in a semiconductor device that uses the AVS power management technology by using the delay monitor circuit.